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 MK1704A
Low EMI Clock Generator
Description
The MK1704A is an upgraded version of the MK1704 and is recommended for all new designs. It offers more reduction in the frequency amplitude peaks and will support frequencies up to 140 MHz. The MK1704A generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock or other clocks for flat panel graphics controllers. The MK1704A uses ICS' proprietary mixture of analog and digital Phase Locked Loop (PLL) technology to synthesize the frequency. It also uses ICS' patented technique to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. ICS offers many other clocks for computers and computer peripherals. Consult ICS when you need to remove crystals and oscillators from your board.
Features
* * * * *
8 pin SOIC package Available in Pb (lead) free package Provides a spread spectrum output clock Supports leading flat panel controllers Accepts a clock input, provides same frequency dithered output 140 MHz, as well as 40 MHz (SVGA) and 65 MHz (XVGA) clocks
* Optimized for higher resolutions that require up to * Peak reduction by 7 dB - 14 dB typical on 3rd - 19th
odd harmonics
* * * *
Low EMI feature can be disabled Operating voltage of 3.3V or 5V Advanced, low power CMOS process See the MK1714-01 for a multiplier with low EMI which can operate from a crystal
Block Diagram
VDD
S1:0 Low EMI Enable
2 PLL Clock Synthesis and Spread Spectrum Circuitry Input Buffer
CLK
Input
GND
MDS 1704A E Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com
MK1704A Low EMI Clock Generator
Pin Assignment
ICLK VDD GND CLK 1 2 3 4 8 7 6 5 NC S0 S1 LEE
Output Clock Selection Table
Input Input Input S1 S0 Min. Nom. Max. Mult.
0 0 1 1 0 1 0 1 60 60 30 40 135 80 40 65 140 120 60 100 x1 x1 x1 x1
Freq. spread vs. CLK
+0.5, -1.5% +0.5, -1.5% Down 2.5% +0.5, -1.5%
8 pin (150 mil) SOIC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
ICLK VDD GND CLK LEE S1 S0 NC
Pin Type
XI Power Power Output Input Input Input Connect to +3.3V or +5V. Connect to ground.
Pin Description
Connect to a clock input as shown in table above.
Clock output equal to input frequency. Low EMI enable. Turns on the spread spectrum when high. Internal pull-up. Frequency select 1 input. Selects input/output clock range per table above. Internal pull-up. Frequency select 0 input. Selects input/output clock range per table above. Internal pull-up. No connect. Do not connect anything to this pin.
External Components
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI the 33 series termination resistor, if needed, should be placed close to the clock output.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected between VDD and GND on pins 2 and 3.
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed.
MDS 1704A E Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com
MK1704A Low EMI Clock Generator
4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed
away from the MK1704A. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Powerup Considerations
To insure proper operation of the spread spectrum generation circuit, some precautions must be taken in the implementation of the MK1704A. 1) An input signal should not be applied to ICLK until VDD is stable. This requirement can easily be met by operating the MK1704A and the ICLK source from the same power supply. 2) LEE should not be enabled (taken high) until after the power supplies and input clock are stable. This requirement can be met by direct control of LEE by system logic; for example, a "power good" signal. Another solution is to leave LEE unconnected to anything but a 0.01 F capacitor to ground. The pullup resistor on LEE will charge the capacitor and provide approximately a one millisecond delay until spread spectrum is enabled. 3) If the input frequency is changed during operation, disable spread spectrum until the input clock stabilizes at the new frequency. LEE should be disabled for 10 s minimum.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1704A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -65 to +150C 175C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.0
Typ.
Max.
+70 +5.5
Units
C V
MDS 1704A E Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com
MK1704A Low EMI Clock Generator
DC Electrical Characteristics
Unless stated otherwise, VDD = 5V, Ambient Temperature 0 to +70C
Parameter
Operating Voltage Supply Current Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Capacitance Nominal Output Impedance Internal Pull-up Resistor
Symbol
VDD IDD VIH VIL VOH VOH VOL CIN ZOUT RPU
Conditions
No load, 3.3V No load, 5V Clock input Clock input IOH = -4 mA IOH = -25 mA IOL = 25 mA S0 pin LEE pin only
Min.
3.0
Typ.
10 15
Max.
5.5
Units
V mA mA V
(VDD/2)+1 VDD-0.4 2.4
VDD/2 VDD/2 (VDD/2)-1
V V V
0.4 7 20 500
V pF k
AC Electrical Characteristics
Unless stated otherwise, VDD = 5V, Ambient Temperature 0 to +70 C
Parameter
Input Frequency
Symbol
Conditions
S1=0, S0=0 S1-0, S0=1 S1=1, S0=0 S1=1, S0=1
Min.
60 60 30 40 20
Typ.
135 80 40 65
Max. Units
140 120 60 100 80 1.5 1.5 MHz MHz MHz MHz % ns ns % % dB
Input Clock Duty Cycle Output Rise Time Output Fall Time Output Clock Duty Cycle Output Clock Frequency Variation from Mean EMI Peak Frequency Reduction Note 1: Measured with 15pF load tOR tOF
Time above VDD/2 0.8 to 2.0V, Note 1 2.0 to 0.8V, Note 1 Time above 1.5V
40
50 1-2.5
60
3rd - 19th odd harmonics
10-16
MDS 1704A E Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com
MK1704A Low EMI Clock Generator
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
150 140 120 40
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram
8 5
CLOCK MK1704A YYWW
1 4
Marking Diagram (Pb free)
8 5
CLOCK MK1704AL YYWW
1 4
Notes: 1. YYWW is the last two digits of the year and week the part was assembled. 2. "L" denotes Pb (lead) free package 3. Bottom Markings: ###### = lot number (origin) = country of origin if not USA
MDS 1704A E Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com
MK1704A Low EMI Clock Generator
Package Outline and Package Dimensions (8 pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters Symbol Min Max
Inches Min Max
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
MK1704A MK1704ATR MK1704ALF MK1704ALFTR
Marking
see page 5
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
8 pin SOIC 8 pin SOIC 8 pin SOIC 8 pin SOIC
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 1704A E Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 120903 tel (408) 297-1201
www.icst.com


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